Embodiments presented herein generally relate to integrated circuit (IC) memory devices, and more specifically, to dynamic random access memory (DRAM) with differential sensing.
DRAM is a type of random access memory which utilizes separate capacitors to store each bit of data based upon the voltage stored in the capacitors. A memory circuit is formed from an array of DRAM cells where all of the cells in a given column of the array are coupled to a single bit line. Similarly, a single word line may serve all the cells in a given row. In this manner, data stored in one of the DRAM cells in the memory circuit can be read from the cell's capacitor through its respective bit line in response to the word line activating the cell.
DRAM cells and circuits may be produced using semiconductor lithography. Modern trends in DRAM production scale DRAMs to ever smaller lithography sizes. As sizes are reduced, it becomes more difficult to maintain reliability and performance as lithography error rates increase.